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ds28e05 1-wire eeprom general description the ds28e05 is a 112-byte user-programmable eeprom organized as 7 pages of 16 bytes each. memory pages can be individually set to write protected or eprom emulation mode through protection byte settings. each part has its own guaranteed unique 64-bit rom identi - fication number (rom id) that is factory programmed into the chip. the ds28e05 communicates over maxim integrateds single contact 1-wire ? interface at overdrive speed with the rom id acting as node address in the case of a multiple-device 1-wire network. applications accessory/pcb identiication medical sensor calibration data storage analog sensor calibration aftermarket management of consumables features single-contact 1-wire interface 112 bytes user eeprom with 1k write cycles programmable write protection and otp eprom emulation modes for user memory unique factory-programmed 64-bit rom id number communicates with host at up to 76.9kbps (overdrive only) operating range: 2.75v to 3.63v, -40 c to +85 c 8kv hbm esd protection (typ) on io pin 3-pin sot23 and 6-pin tsoc packages 19-6568; rev 1; 1/14 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/ds28e05.related . typical application circuit 1-wire is a registered trademark of maxim integrated products, inc. io r pup v cc c gnd ds28e05 downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 2 electrical characteristics (t a = -40c to +85c, unless otherwise noted.) (note 1) io voltage range to gnd ...................................... -0.5v to 4.0v io sink current ................................................................. 20ma operating temperature range .......................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -55c to +125c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ...................................... +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter symbol conditions min typ max units io pin: general data 1-wire pullup voltage v pup (note 2) 2.75 3.63 v 1-wire pullup resistance r pup v pup = 3.3v 10% (note 3) 300 1500 ? input capacitance c io (notes 4, 5) 1500 pf input load current i l io pin at v pup 5 20 a high-to-low switching threshold v tl (notes 6, 7) 0.65 x v pup v input low voltage v il (notes 2, 8) 0.5 v low-to-high switching threshold v th (notes 6, 9) 0.75 x v pup v switching hysteresis v hy (notes 6, 10) 0.3 v output low voltage v ol i ol = 4ma (note 11) 0.4 v recovery time t rec r pup = 1500? (notes 2, 12) 5 s time slot duration t slot (notes 2, 13) 13 s io pin: 1-wire reset, presence detect cycle reset low time t rstl (note 2) 48 80 s reset high time t rsth (note 14) 48 s presence detect sample time t msp (notes 2, 15) 8 10 s io pin: 1-wire write write-zero low time t w0l (notes 2, 16) 8 16 s write-one low time t w1l (notes 2, 16) 1 2 s io pin: 1-wire read read low time t rl (notes 2, 17) 1 2 - s read sample time t msr (notes 2, 17) t rl + 2 s eeprom programming current i prog v pup = 3.63v (notes 5, 18) 400 a programming time for a 16-bit segment t prog (note 19) 16 ms write/erase cycling endurance n cy t a = +85 c (notes 20, 21) 1000 data retention t dr t a = +85 c (notes 22, 23, 24) 10 years downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) (t a = -40c to +85c, unless otherwise noted.) (note 1) note 1: limits are 100% production tested at t a = +25c and/or t a = +85c. limits over the operating temperature range and rel - evant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: system requirement. note 3: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. note 4: typical value represents the internal parasite capacitance when v pup is first applied. once the parasite capacitance is charged, it does not affect normal communication. note 5: guaranteed by design and/or characterization only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage, which is a function of v pup , r pup , 1-wire timing, and capacitive loading on io. lower v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on io, a logic 0 is detected. note 8: the voltage on io must be less than or equal to v ilmax at all times the master is driving io to a logic 0 level. note 9: voltage above which, during a rising edge on io, a logic 1 is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io must drop by at least v hy to be detected as logic 0. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: applies to a single device attached to a 1-wire line. note 13: defines maximum possible bit rate. equal to 1/(t w0lmin + t recmin ). note 14: an additional reset or communication sequence cannot begin until the reset high time has expired. note 15: interval after t rstl during which a bus master can read a logic 0 on io if there is a ds28e05 present. the power-up pres - ence detect pulse could be outside this interval but will be complete within 2ms after power-up. note 16: in figure 10 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 17: in figure 10 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input-high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 18: current drawn from io during the eeprom programming interval, during which the voltage at io must n ot drop below 1.8v. this condition is met with r pupmax over the entire v pup range. note 19: the t prog interval begins immediately after the trailing rising edge on io for the last time slot of the release byte for a valid write memory sequence. interval ends once the devices self-timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l . note 20: write-cycle endurance is tested in compliance with jesd47g. note 21: not 100% production tested; guaranteed by reliability monitor sampling. note 22: data retention is tested in compliance with jesd47g. note 23: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. note 24: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-term storage at elevated tem - peratures is not recommended. downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 4 pin descriptions pin conigurations detailed description the ds28e05 combines 896 bits of user eeprom orga - nized as seven 128-bit pages, 64 bits of administrative data memory, and a 64-bit rom id in a single chip. data is transferred serially through the 1-wire protocol, which requires only a single data lead and a ground return. the user memory can have unrestricted write access (fac - tory default), or can be write protected or put in eprom emulation mode. write protection prevents changes to the memory data. eprom emulation mode logically ands memory data with incoming new data, which allows changing bits from 1 to 0, but not vice versa. by chang - ing one bit at a time this mode could be used to create nonvolatile nonresettable counters. for more details refer to application note 5042: implementing nonvolatile, nonresettable counters for embedded systems . the devices 64-bit rom id can be used to electronically identify the equipment in which the ds28e05 is used. the rom id guarantees unique identification and is also used to address the device in a multidrop 1-wire network environment, where multiple devices reside on a com - mon 1-wire bus and operate independently of each other. applications include accessory/pcb identification, medi - cal sensor calibration data storage, analog sensor calibra - tion, and after-market management of consumables. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds28e05. the ds28e05 has three main data compo - nents: seven 128-bit pages of user eeprom, 64 bits of administrative data memory, and a 64-bit rom id. figure 2 shows the hierarchic structure of the 1-wire protocol. the bus master must first provide one of the five rom function commands: read rom, match rom, search rom, skip rom, or resume communication. the protocol required for these rom function commands is described in figure 8 . after a rom function command is successfully executed, the memory functions become accessible and the master can select one of the two memory function commands. the function protocols are described in figure 6 . all data is read and written least significant bit first. 64-bit rom id each ds28e05 contains a unique rom id that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits. see figure 3 for details. the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4 . pin name function sot23 tsoc 2 3C6 n.c. not connected 1 2 io 1-wire bus interface. open-drain signal that requires an external pullup resistor. 3 1 gnd ground reference n.c. io gnd n.c. n.c. n.c. tsoc top view + 54 6 23 1 ds28e05 ds28e05 n.c. 1 3g nd io + 0dr r sot23 top view 2 downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 5 figure 1. block diagram figure 2. hierarchical structure for 1-wire protocol figure 3. 64-bit rom id the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1-wire cyclic redundancy check is available in application note 27: understanding and using cyclic redundancy checks with maxim ibutton? products . the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is entered. after the last bit of the serial number has been entered, the shift reg - ister contains the crc value. shifting in the 8 bits of the crc returns the shift register to all 0s. ibutton is a registered trademark of maxim integrated products, inc. ds28e05 1-wire function control 1-wire net parasite power 64-bit rom id administrative data (64 bits) user eeprom 7 pages of (128 bits each) memory function control available commands: data field affected: read rom match rom search rom skip rom resume 64-bit rom id, rc-flag64-bit rom id, rc-flag 64-bit rom id, rc-flag rc-flag rc-flag 1-wire rom function commands write memoryread memory user memory, administrative dat a user memory, administrative dat a ds28e05-specific memory function commands command level: ds28e05 msb 8-bit crc code 48-bit serial number msb lsb msb lsblsb 8-bit family code (0dh) msb lsb downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 6 table 1. memory resources table 2. address to segment mapping memory resources the memory of the ds28e05 consists of user memory, administrative data, and a rom id. table 1 shows the size, access mode and purpose of the various memory areas. brackets around an access mode indicate possible restrictions, such as write protection or read protection. the memory is organized as 8 pages of 16 bytes each ( figure 5 ). each page consists of 8 segments. table 2 shows how the segments relate to a memory address. pages 0 to 6 are the user memory. page 7 contains the administrative data and the rom id. the function memory locations 0074h to 0075h depends on the code in the factory word (addresses 0076h to 0077h). the manufacturer id can be a customer-supplied identification code that assists the application software in identifying the product the ds28e05 is associated with. contact the factory to set up and register a custom manufacturer id. write protection or eprom emulation mode is activated through the write memory command by writing to the corresponding locations (ppa to ppd) in the administra - tive data page. once a protection is activated, it cannot figure 4. 1-wire crc generator legend: (5fh) designates memory location 5fh. text without brackets refers to the register name. name size (bytes) access mode purpose user memory (eeprom) 112 read, (write) application-speciic data storage administrative data 8 read, (write), internal read page protection settings, factory bytes, user bytes/manufacturer id rom id 8 read, internal read 1-wire network device address segment 7 segment 6 segment 5 segment 4 segment 3 segment 2 segment 1 segment 0 b1 b0 b1 b0 b1 b0 b1 b0 b1 b0 b1 b0 b1 b0 b1 b0 page 0 (0fh) (08h) (00h) page 1 (1fh) (18h) (10h) page 2 (2fh) (28h) (20h) page 3 (3fh) (38h) (30h) page 4 (4fh) (48h) (40h) page 5 (5fh) (58h) (50h) page 6 (6fh) (68h) (60h) page 7 rom id factory man. id/u. ppd ppc ppb ppa 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 7 figure 5. user memory map be reversed. once the page protections are finalized, the copy lock nibble (73h, upper) should be set to prevent changes. the protection settings are read-accessible through the read memory command. see the memory function commands section for command flow details. the rom id uniquely identifies each individual ds28e05 and serves as network address in a mutidrop 1-wire network. the rom id can be read through the rom function commands; it is also read-accessible as part of the 8th memory page. the family code is stored at the lower address (78h). memory function commands the memory function flowchart ( figure 6 ) describes the protocols to access the memory of the ds28e05. the memory is written in segments of 2 bytes. address range type description protection codes 0000h to 000fh r/(w) user memory page 0 0010h to 001fh r/(w) user memory page 1 0020h to 002fh r/(w) user memory page 2 0030h to 003fh r/(w) user memory page 3 0040h to 004fh r/(w) user memory page 4 0050h to 005fh r/(w) user memory page 5 0060h to 006fh r/(w) user memory page 6 0070h* r/(w) page protection ppa, lower nibble: page 0; upper nibble: page 1 0h: open (factory default); ah: eprom mode; all other codes: write protected 0071h* r/(w) page protection ppb, lower nibble: page 2, upper nibble: page 3 0h: open (factory default); ah: eprom mode; all other codes: write protected 0072h* r/(w) page protection ppc, lower nibble: page 4, upper nibble: page 5 0h: open (factory default); ah: eprom mode; all other codes: write protected 0073h* r/(w) page protection ppd, lower nibble: page 6, upper nibble: copy lock 0h: open (factory default); ah: eprom mode; all other codes: write protected copy lock 0h: open (factory default); all other codes: page protection locations ppa,ppb,ppc,ppd write protected. prevents changes to the page modes. 0074h to 0075h r/(w) manufacturer id/user bytes 0076h to 0077h r factory word. set at factory. c3a9h: addresses 0074h to 0075h are user bytes. 3c56h: addresses 0074h to 0075h are write protected and hold a manufacturer id. 0078h to 007fh r rom id, alternate readout (family code at address 0078h) *once a nibble is programmed to anything other than 0h, the nibble cannot be changed. downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 8 figure 6. memory functions flowchart master tx starting address t[15:0] yy y n y f0h read memory? n n address < 0080h? master tx reset? master tx reset? end of memory? master tx memory function command ds28e05 sets memory address = (t[15:0]) master rx (reads back) 2 data bytes and verifies master rx data byte from memory address ds28e05 increments address counter master rx ?1?s from rom functions flowchart (figure 8) to rom functions flowchart (figure 8) master tx parameter byte yy y 55h write memory? n master tx ffh release byte? parameter byte and ffh byte valid? master tx ffh byte master waits 1 x t prog * master rx cs byte master tx 2 data bytes master tx reset? segment # = 7? y n ny master tx reset? *1-wire idle high for power. y n n n master rx ?1?s n y n ds28e05 increments address counter downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 9 write memory [55h] the write memory command is used to program one or more contiguous 2-byte segments of a memory page. this com - mand is applicable only to memory locations that are not write protected. the parameter byte specifies the page and segment number where the writing begins. the new segment data is transmitted in the sequence b0, b1. table 2 shows the how these bytes map to the addressed memory page. the command flow allows writing one or multiple adjacent segments within a page. to safeguard against transmission errors, the ds28e05 supports read-after-wr ite verification. in case of data error, the master aborts the command by issuing a 1-wire reset. to start the transfe r to eeprom the master must transmit a release byte (ffh). after the programming time is over, the ds28e05 transmits a cs byte. if a page is in eprom emulation mode, the new segment data is the bitwise and of the segment data in memo ry and the new data provided with the command. bits 6:4: memory page selection (page #). these bits specify the memory page that is to be written to. valid memory page numbers are 000b (page 0) to 111b (page 7). bits 3:1: starting segment selection (seg #). these bits specify the location within the selected memory page where the writing begins. for pages 0 to 6 valid segment numbers are 000b (start of memory page) to 111b ( last segment of memory page). valid segment numbers for page 7 are 000b, 001b, and 010b. table 3. parameter byte bitmap note: the bits marked as 0 must be transmitted as 0 for the parameter byte to be valid. write memory command code 55h parameter byte target page selection, starting segment number (table 3). restrictions the memory page must not be write protected. protocol variations writing within a page. writing through the end of the page. error conditions invalid parameter byte.the memory page is write protected. cs byte aah = success. 33h = the command failed because the page is write protected. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 page # seg # 0 downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 10 read memory [f0h] the read memory command is used to read the memory. the command needs a 16-bit starting address ta1, ta2. the parameter byte specifies the lower address byte (ta1, t[6:0]) where the reading begins. after the pa rameter byte, the master transmits ta2 (t[15:8]), which must be 00 to be valid. the reading can start at any valid sta rting address and continue trough the end of the memory. if memory page 7 is read and the master continues reading, th e resulting data is ffh. the master can end the read memory command at any time by issuing a reset pulse. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds28e05 is a slave device. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware coniguration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three- state outputs. the 1-wire port of the ds28e05 is open drain with an internal circuit equivalent to that shown in figure 7 . table 4. parameter byte bitmap note: the bit marked as 0 must be transmitted as 0 for the parameter byte to be valid. figure 7. hardware configuration read memory command code f0h parameter byte starting memory address (table 4). restrictions none. this command can be issued at any time. protocol variations none. error conditions invalid parameter byte. cs byte n/a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 ta1 rx r pup i l v pup bus master open-drain port pin 100 mosfet tx rxtx data ds28e05 1-wire port rx = receive tx = transmit downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 11 a multidrop bus consists of a 1-wire bus with multiple slaves attached. the ds28e05 supports overdrive speed of 76.9kbps (max) only and cannot be used together with standard speed or dual-speed 1-wire slaves on the bus. the value of the pullup resistor primarily depends on the 1-wire pullup voltage, network size and load conditions. the ds28e05 requires a pullup resistor of maximum 1.5k?. the idle state for the 1-wire bus is high. if for any reason a transaction must be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16s, one or more devices on the bus could be reset. transaction sequence the protocol for accessing the ds28e05 through the 1-wire port is as follows: ? initialization ? rom function command ? memory function command ? transaction data initialization all transactions on the 1-wire bus begin with an initializa - tion sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the pres - ence pulse lets the bus master know that the ds28e05 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. 1-wire rom function commands once the bus master has detected a presence, it can issue one of the five rom function commands that the ds28e05 supports. all rom function commands are 8 bits long. a list of these commands follows (see the flow - chart in figure 8 ). read rom [33h] the read rom command allows the bus master to read the ds28e05s rom id (8-bit family code, unique 48-bit serial number, and 8-bit crc). this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the family code and 48-bit serial number as read by the master are unlikely to match the crc. match rom [55h] the match rom command, followed by a 64-bit rom id, allows the bus master to address a specific ds28e05 on a multidrop bus. only the ds28e05 that exactly matches the 64-bit rom id responds to the following memory function command. all other slaves wait for a reset pulse. this command can be used with a single or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their rom id numbers. by taking advantage of the wired-and property of the bus, the master can use a pro - cess of elimination to identify the id of all slave devices. for each bit of the id number, starting with the least sig - nificant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its id number bit. on the second slot, each slave device participating in the search outputs the complemented value of its id number bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participating in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choos - ing which state to write, the bus master branches in the search tree. after one complete pass, the bus master knows the rom id number of a single device. additional passes identify the id numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. skip rom [cch] this command can save time in a single-drop bus sys - tem by allowing the bus master to access the memory functions without providing the 64-bit rom id. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom com - mand, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 12 figure 8. rom functions flowchart ds28e05 tx presence pulse bus master tx reset pulse bus master tx rom function command ds28e05 tx crc byte ds28e05 tx family code (1 byte) ds28e05 tx serial number (6 bytes) rc = 0 master tx bit 0 rc = 0 rc = 0 rc = 0 y y yy y y y 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? n cch skip rom command? n rc = 1 master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y rc = 1 from memory function flowchart (figure 6) to memory functions flowchart (figure 6) ds28e05 tx bit 0 ds28e05 tx bit 0 master tx bit 0 bit 1 match? bit 63 match? ds28e05 tx bit 1 ds28e05 tx bit 1 master tx bit 1 ds28e05 tx bit 63 ds28e05 tx bit 63 master tx bit 63 y rc = 1? y a5h resume command? n n y y master tx reset? n downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 13 resume command [a5h] to maximize the data throughput in a multidrop environ- ment, the resume command is available. this command checks the status of the rc bit and, if it is set, directly transfers control to the memory functions, similar to a skip rom command. the only way to set the rc bit is through successfully executing the match rom or search rom command. once the rc bit is set, the device can repeatedly be accessed through the resume command. accessing another device on the bus clears the rc bit, preventing two or more devices from simultaneously responding to the resume command. 1-wire signaling the ds28e05 requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all falling edges. the ds28e05 communicates at overdrive speed only. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v il(max) past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 9 as , and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v il(max) is relevant for the ds28e05 when determining a logical level, not triggering any events. figure 9 shows the initialization sequence required to begin any communication with the ds28e05. a reset pulse followed by a presence pulse indicates that the ds28e05 is ready to receive data, given the correct rom and memory function command. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. after the bus master has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor. when the threshold v th is crossed, the ds28e05 waits and then transmits a presence pulse by pulling the line low. to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . read-/write-time slots data communication with the ds28e05 takes place in time slots that carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 10 illustrates the definitions of the write- and read-time slots. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below the threshold v tl , the ds28e05 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write- one low time t w1l(max) is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0l(min) is expired. for the most reliable communication, the voltage on the data line should not exceed v il(max) during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds28e05 needs a recovery time t rec before it is ready for the next time slot. figure 9. initialization procedure: reset and presence pulse resistor master ds28e05 t rstl t rsth master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v il(max) 0v t f t rec t msp downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 14 slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds28e05 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds28e05 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. figure 10. read/write timing diagrams resistor master resistor master resistor master ds28e05 v pup v ihmaster v th v tl v il(max) 0v t f v pup v ihmaster v th v tl v il(max) 0v t f v pup v ihmaster v th v tl v il(max) 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slotwrite-zero time slot read-data time slot downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 15 the sum of t rl + (rise time) on one side and the internal timing generator of the ds28e05 on the other side define the master sampling window (t msr(min) to t msr(max) ), in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msr(max) . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds28e05 to get ready for the next time slot. note that t rec specified herein applies only to a single ds28e05 attached to a 1-wire line. for multidevice configurations, t rec must be extended to accommodate the additional 1-wire device input capacitance. improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possible only during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are susceptible to noise of various origins. depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search rom command coming to a dead end or cause a device- specific function command to abort. the ds28e05 uses a 1-wire front-end with built-in hysteresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v tl , it is not recognized ( figure 11 ). 1-wire communication examples see table 5 and table 6 for the 1-wire communication legend and data direction codes. figure 11. noise suppression scheme table 5. 1-wire communication legend table 6. data direction codes symbol description rst 1-wire reset pulse generated by master pd 1-wire presence detect pulse generated by slave select command and data to satisfy the rom function protocol pb parameter byte cs command success indicator release ffh byte sent by the master to start a write activity in the slave wm command write memory rm command read memory transfer of n bytes transfer of as many bytes as are needed to reach the end of the page data transfer of 2 bytes segment data ff loop indeinite loop where the bus master reads ffh bytes master-to-slave slave-to-master master waits (1-wire idle high) v pup v th v tl v hy 0v downloaded from: http:///
ds28e05 1-wire eeprom www.maximintegrated.com maxim integrated 16 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information 1-wire communication examples (continued) + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *future productcontact factory for availability. part temp range pin-package ds28e05r+t* -40oc to +85oc 3 sot23 (3k pcs) ds28e05p+ -40oc to +85oc 6 tsoc ds28e05p+t -40oc to +85oc 6 tsoc (4k pcs) package type package code outline no. land pattern no. 3 sot23 u3+2 21-0051 90-0179 6 tsoc d6+1 21-0382 90-0321 wait t prog rst wm pb ffh ffh write memorywriting within a page, not reaching the end of the page. pd select data data data data ffh ffh 00h data data release repeat cs = aah rst rst rm read memorystarting at address 33h, reading 6 bytes pd select rst ff loop ff loop ff loop wait t prog rst wm pb writing through the end of the page. pd select release repeat cs = aah wait t prog rst wm pb writing fails with protection error pd select release cs = 33 h rst wm invalid parameter byte pd select pb = 7eh ff loop rst rm invalid parameter byte pd select pb = 80h rst <6 bytes> 00h 00h <10 bytes> rst rm starting at the manufacturer id, reading beyond the end of memory pd select pb = 76h pb = 33h downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ds28e05 1-wire eeprom ? 2014 maxim integrated products, inc. 17 revision history revision number revision date description pages changed 0 12/12 initial release 1 1/14 expanded v pup (min) to 2.75v and v il (max) to 0.5v 1, 2 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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